1. Field of the Invention
The present invention relates to semiconductor device fabrication, and more particularly to a structurally reinforced semiconductor structure for a semiconductor device.
2. Description of the Related Art
Typically, a plurality of semiconductor components are manufactured from a single semiconductor wafer. The semiconductor wafer is portioned into a plurality of die or chips, wherein adjacent chips are separated by scribe lines. The manufacturing process is designed so all the chips on a single semiconductor wafer are identical. Once the transistor circuitry and associated metal interconnects have been fabricated in the active area, the semiconductor wafers are sawed along the scribe lines to separate or singulate the semiconductor wafer into a plurality of semiconductor chips. The chips are then packaged, tested and shipped to customers.
To assess the electrical properties of elements constituting a chip, however, a predetermined pattern of measuring elements or test elements (referred to as a test element group (TEG)) is formed on a scribe line area of a semiconductor wafer. The TEG is electrically tested for determining whether elements are suitably formed in the chips formed on the wafer.
Since the TEG is formed using the same process as a process for forming elements in integrated circuit chips, testing the electrical properties of the TEG can be similar or even identical to test the electrical properties of the elements formed in the chips. Accordingly, the properties of the chips can be correctly deduced by testing the TEG. Once the properties have been tested, there is no reason to retain the TEG. Thus the TEG can be formed in a sacrificial area of the wafer. Hence, the TEG is disposed in a scribe line area of the wafer to prevent a decrease in the number of integrated circuit chips could be produced from the wafer.
FIG. 1 illustrates a top view of a part of a semiconductor wafer 5 comprising a scribe line area 40 separating two active areas 10 and 20 where the transistor circuitry and associated metal interconnects input pads, output pads, and MOS elements (not shown) are formed. In the scribe line area 40, test element groups (TEGs) 30 are disposed in the scribe line area 40 substantially in a linear manner. The TEGs 30 may include TEG modules each having a plurality of MOS elements and associated metal interconnects. FIG. 2 illustrates a cross-section taken along line 2-2 of FIG. 1, but only the associated metal interconnects formed in the TEGs 30 are shown here, for simplicity. As shown in FIG. 2, a top portion of the TEGs 30 is illustrated, including a plurality of dielectric layers 42, 44 and 46, each having metal components 32, functioning as conductive pads or conductive lines, and metal components 34, functioning as vias for connecting components 32 and/or MOS elements (not shown) thereunder. However, with the trend of size reduction of integrated circuits, copper metal incorporating low-k dielectrics having a dielectric constant (k) less than that of the conventional silicon oxide (SiO2) dielectric material (about 4.0) has been adopted in such conductive interconnects of integrated circuits to reduce or prevent increases of RC product (resistance×capacitance) of the interconnects formed in the integrated circuits. Unfortunately, the low-k dielectric materials have disadvantage characteristics such as low mechanical strength, poor dimensional stability, poor temperature stability, high moisture absorption and so on. Therefore, once low-k dielectric materials are used in the metal interconnects of the TEGs 30, microcracking occurs during die sawing or separating along a scribe line 50 (i.e. the dotted line 2-2) and migrates to the active regions of the chips, thereby may seriously damage the circuitry fabricated in each of the chips.